CERN Accelerating science

ALICE (A Large Ion Collider Experiment) is the heavy-ion experiment at the Large Hadron Collider (LHC) at CERN; it is designed to address the physics of strongly interacting matter and in particular the properties of quark-gluon plasma. The experiment took data from 2009 to 2018 (LHC Run1 and Run 2) and went under a major upgrade during the LHC Long Shutdown 2 (2018- 2021). Starting from 2022 detector is back in operation and it is foreseen to keep performing measurements up to 2032. A pillar of the ALICE future upgrade program is the improvement of the Inner Tracking System (ITS2) performance by the replacement of its three innermost layers (ITS3) during the LHC Long Shutdown 3, taking place between 2026 and 2028. The proposal is based on a vertex detector consisting of three cylindrical concentric layers composed by curved wafer-scale silicon sensors, built on CMOS Monolithic Active Pixel Sensors (MAPS) with the sensor matrix and readout integrated in a single chip. The first detector layer will be positioned at a radial distance from the interaction point of 18 mm. The new detector will present a significant reduction of the material budget, from 0.36% X$_0$ (in ITS2) to 0.05% X$_0$ per layer, thus improving the vertexing and tracking performance, especially for particles with low transverse momentum (p$_T$ < 1 GeV/c). $\newline$ The main scope of this thesis is to report on the activities associated with the characterization of bent MAPS, fabricated with TowerJazz 180 nm CMOS Technology, as well as the development of tools and techniques dedicated to bend accurately such devices. $\newline$ Extensive characterization of a single ALPIDE chip (used for the current ITS2), positioned flat and bent down to the intended radius for the innermost layer of the ITS3 (18 mm), was carried out in order to evaluate its performance under the mechanical stress involved in the bending process. The measurement of the main variables steering the chip functioning was performed by evaluating their behavior over the time and through the variation of different in-pixel circuit parameters. The results were compared for both geometries. These studies aimed to demonstrate that ALPIDE functionalities are preserved despite the curvature effects. $\newline$ An important component in the investigation of a detector performance is the realization of a so-called test-beam experiment. The data acquired during the first ever in-beam characterization of a bent MAPS, performed in a test- beam campaign at the DESY II test-beam facility in June 2020, were analyzed and systematically compared with data taken with a flat ALPIDE. The study had the main scope to evaluate the sensing performance of a bent chip through the variation of the working point defined by front-end parameters and contrast it with the results of an originally flat sensor. $\newline$ The analysis of efficiency, cluster size and preliminary position resolution was also performed for an experiment realized in July 2021 at CERN SPS facility, where a set of six ALPIDE chips were bent at the foreseen ITS3 layer radii, forming the so-called micro-ITS3. The objective was the simultaneous in-beam characterization of several concentrically arranged bent ALPIDE chips, thus modelling the tracking layers of the future ITS3. $\newline$ An additional study was done from measurements where a copper target was introduced in the center of the detector barrel of the micro-ITS3 in order to mimic particles emerging from a real collision. Through this activity the possibility to reconstruct tracks and vertices from hadronic interactions in a geometrical configuration very close to the next full ITS (including ITS3) has been explored and demonstrated. $\newline$ The tests on small sensors have opened the way to the investigation of a large scale sensor. The “super-ALPIDE” project has the goal to assembly a detector with geometry similar to one half-layer of the ITS3, using a working sensor with large dimensions made of a matrix of not diced ALPIDE chips. The concept of the super-ALPIDE design, including the components and mechanical structures implemented for readout and support, is presented in this thesis. Techniques and tools employed to perform sensor bending, parts assembly and wired interconnections are described in detail. $\newline$ Another subject, within the context of the ITS upgrade R&D, is the prelim- inary study of new sensor prototypes based on TPSCo 65 nm CMOS process, the first choice of the technology for the implementation of the wafer-scale sen- sor, which allows for more than four-fold increase of the number of transistors per pixel compared to the older 180 nm and higher spatial resolution resulting from the possibility to fabricate smaller pixels. A first submission in TPSCo 65 nm was done as a Multi Layer Reticle (MLR1). An overview of the three main prototype structures composing MLR1 (Digital Pixel Test Structure, CE65 and Analogue Pixel Test Structure) is given in the last chapter of this thesis. The APTS op-amp, modified with gap version with DC coupled in-pixel architec- ture and 10 μm pitch, was tested in laboratory in order to characterize this chip flavor. The response of the pixels front-end was monitored by the measurement at different chip bias settings to evaluate the influence of the main parameters of the in-pixel circuit on the signal processing. The study of the device charge collection properties was performed through measurements with X-rays emitted by an $^{55}$Fe source.