CERN Accelerating science

The ITS3 upgrade of the ALICE experiment at the Large Hadron Collider (LHC) represents a significant leap in vertex detector technology. Scheduled for installation during the third LHC Long Shutdown (LS3, 2026-2029), this upgrade will replace the three innermost layers of the current system with curved, wafer-scale, ultra-thin silicon sensors arranged in truly cylindrical geometries. This novel configuration aims at reducing the material budget, and enhancing the tracking performance. Achieving this breakthrough requires the adoption of innovative approaches, some of which are unprecedented in high-energy physics. These include low-speed air-flow cooling, bent silicon, stitching technology, and the deployment of a new sensor design based on a 65 nm CMOS imaging process. Moving to a 65 nm process requires a technology qualification phase, dedicated to process optimisation and charge collection performance evaluation with respect to pixel size, pixel design and radiation load. This thesis focuses on the characterization of an analog prototype sensor developed using the 65 nm technology. An extensive series of measurements was conducted, including laboratory experiments using an 55Fe source and beam tests, to assess charge collection efficiency, detection efficiency, and radiation tolerance. Several variants of the prototype were tested to identify the optimal design for the ITS3 application. Complementing the experimental work, a detailed simulation study was undertaken to model the charge collection process. The simulation workflow involved calculating the sensor’s electric field using TCAD simulations and employing this field in Garfield++ to simulate charge transport and collection mechanism. The charge collection information is then used to simulate the chip reponse to X-rays coming from the 55Fe source. The simulated results show a good agreement with the experimental data, allowing for a deep understanding of the device. The findings presented in this thesis highlight the potential of MAPS technology for high-energy particle detection. The 65 nm CMOS imaging process was conclusively validated as a robust solution for the ITS3 upgrade, while the developed simulation framework demonstrates its potential as a powerful tool for the design and optimization of MAPS sensors. Beyond the ITS3, these technological advancements and methodologies hold promise for future applications in high-energy physics and other applications.